The present disclosure relates to a substrate treating apparatus for depositing a phase-change layer of a phase change random access memory (PRAM) and a substrate treating method, and more particularly, to a substrate treating apparatus and method for manufacturing a phase-change layer having superior deposition characteristics.
The next generation non-volatile memories for supplementing faults of existing non-volatile memories such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and flash memories are being proposed. Ferroelectrics random access memories (FRAMs), magnetic random access memories (MRAMs), phase-change random access memories (PRAMs), and the like may be used as the next generation non-volatile memories.
Particularly, the phase-change RAMs (PRAMs) that have received great attention lately as one of the next generation non-volatile memories may be manufactured by using germanium-antimony-tellurium (GST; Ge2Sb2Te5) thin film as a main component. Here, phase-change RAM (PRAM) technologies may be technologies using an optical and electrical switching phenomenon between amorphous and crystalline phases through reversible transition from a crystalline state into an amorphous state that relates to resistivity transition of a film material. That is, a resistance or current difference between the amorphous and crystalline phases according to electrical signals may be introduced as the concept of memory. The GST thin film may be deposited through physical vapor deposition (PVD). In recent years, for reasons of commercial high-speed manufacturing and performance, the GST thin film may be deposited by using methods such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
However, it may be difficult to grow a phase-change layer that is the high quality GST thin film at a low temperature through the CVD and ALD. Particularly, when the phase-change layer is deposited after a bottom electrode is formed, following limitations may occur.
The above-described limitations will be described with reference to FIG. 1 that illustrates a cross-section of a phase-change memory including the phase-change layer.
First, in a process of depositing a phase-change memory on a substrate, a dielectric 200 is deposited on a substrate 100. A bottom electrode contact hole is formed on the dielectric 200 by using a mask pattern to deposit a nitride layer such as TiN or TiSiN.
Thereafter, unnecessary portions remaining except for a contact hole in which a bottom electrode 300 will be formed may be removed by an etching process to form the bottom electrode 300. Then, PVD or CVD may be performed on the bottom electrode 300 and the dielectric 200 to successively grow a phase-change layer 400 and an upper electrode 500.
As described above, the etching process has to be performed before the phase-change layer is deposited on the nitride layer. Here, an oxide layer and remaining materials which are generated after the etching process is performed may serve as a cause of a reduced switching rate of the phase-change memory PRAM. To improve the above-described limitation, a surface of the substrate may be treated by using H2 plasma.
However, when the H2 plasma surface treatment is performed as described above, hydrogen H may be bonded to surfaces of the thin films of the bottom electrode and the dielectric 200. In the case where the phase-change layer 400 is deposited by the PVD, an influence due to the bonding of the hydrogen H on the surfaces of the thin films may not be so large when the phase-change layer is deposited. However, in the case where the phase-change layer 400 is deposited by the CVD, deposition characteristics due to the bonding of the hydrogen H on the surfaces of the thin films may be changed. That is, deposition characteristics of the phase-change layer 400 due to the bonding of the hydrogen H on the surfaces of the thin films may be changed to significantly affect an incubation time and directivity, thereby having a bad influence on mass productivity.    PRIOR ART DOCUMENTS: Korean Patent publication No. 10-2009-0091107